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HD151TS303RP
Spread Spectrum Clock for EMI Solution
REJ03D0811-0600 (Previous: ADE-205-656E) Rev.6.00 Apr 07, 2006
Description
The HD151TS303 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution.
Features
* * * * Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz) XIN x 1/2 clock frequency with spread spectrum modulation @3.3 V 1 copy of reference clock out @3.3 V Programmable spread spectrum modulation (0.25%, 0.5%, 1.5% central spread modulation and spread spectrum disable mode.) * SOP-8pin * Ordering Information
Part Name HD151TS303RPEL Package Type SOP-8 pin (JEDEC) Package Code (Previous code) PRSP0008DD-C (FP-8DCV) RP Package Abbreviation Taping Abbreviation (Quantity) EL (2,500 pcs / Reel)
Note: Please consult the sales office for the above package availability.
Key Specifications
* * * * Supply voltages : VDD = 3.3 V0.165 V Ta = 0 to 70C operating range Clock output duty cycle = 505% Cycle to cycle jitter = 250 ps typ.
Block Diagram
VDD GND
CLKOUT(48MHz typ.) XIN OSC XOUT R=1 M 1/n SSC Modulator SEL0 SEL1 1/m Synthesizer 1/2 SSCCLKOUT(24MHz typ.)
R=100 k
Mode Control
R=100 k
Rev.6.00 Apr 07, 2006 page 1 of 8
HD151TS303RP
Pin Arrangement
SSCCLKOUT
1
8
SEL1
VDD
2
7
CLKOUT
GND
3
6
SEL0
XIN
4
5
XOUT
(Top view)
SSC Function Table
SEL1 :0 Spread Percentage 00 +0.5% 01 1.5% 10 SSC OFF 11 0.25% Note: 1.5% SSC is selected for default by internal pull-up & down resistors.
Clock Frequency Table
XIN (MHz) SSCCLKOUT (MHz) 48 24*1 24 12*1 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. CLKOUT (MHz) 48*2 24*2
Pin Descriptions
Pin name GND VDD CLKOUT SSCCLKOUT XIN XOUT SEL0 SEL1 No. 3 2 7 1 4 5 6 8 Type Ground Power Output Output Input Output Input Input Description GND pin Power supplies pin. Normally 3.3 V. Normally 3.3 V reference clock output. Spread spectrum modulated clock output. This pin outputs 1/2 frequency of input frequency. Oscillator input. Oscillator output. SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 k). SSC mode select pin. LVCMOS level input. Pull-down by internal resistor (100 k).
Rev.6.00 Apr 07, 2006 page 2 of 8
HD151TS303RP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Symbol VDD VI VO IIK IOK IO Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -50 -50 50 0.7 Tstg -65 to +150 Unit V V V mA mA mA W C Conditions
VI < 0 VO < 0 VO = 0 to VDD
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature Input clock duty cycle Symbol VDD VIH VIL Ta Min 3.135 -0.3 2.0 -0.3 0 45 Typ 3.3 -- -- -- -- 50 Max 3.465 VDD+0.3 VDD+0.3 0.8 70 55 Unit V V V V C % Conditions
DC Electrical Characteristics
Ta = 0 to 70C, VDD = 3.3 V5%
Item Input low voltage Input high voltage Input current Symbol VIL VIH II Min -- 2.0 -- -- Typ -- -- -- -- Max 0.8 -- 10 100 Unit V V A Test Conditions
VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins 20% - 80% SEL0, SEL1 XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V
Input slew rate Input capacitance Operating current
CI
1 -- --
-- -- 7
4 4 --
V / ns pF mA
DC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 0 to 70C, VDD = 3.3 V5%
Item Output voltage Output current*1 Note: Symbol VOH VOL IOH IOL Min 3.1 -- -- -- Typ -- -- -40 40 Max -- 50 -- -- Unit V mV mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.5 V VOL = 1.5 V
1. Parameters are target of design. Not 100% tested in production.
Rev.6.00 Apr 07, 2006 page 3 of 8
HD151TS303RP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter *1, 2 Symbol tCCS Min -- -- -- -- Output frequency *1, 2 23.8 23.7 23.4 23.8 47.3 Slew rate*1 Clock duty cycle *1 Output impedance *1 Spread spectrum *1 modulation frequency tSL 1.0 45 -- -- Typ | 250 | | 250 | | 250 | | 250 | -- -- -- -- -- -- 50 30 33 Max | 300 | | 300 | | 300 | | 300 | 24.2 24.3 24.6 24.2 48.7 -- 55 -- -- V/ns % KHz MHz Unit ps Test Conditions SSCCLKOUT, Fig1, 24 MHz SSCCLKOUT, Fig1, 24 MHz SSCCLKOUT, Fig1, 24 MHz CLKOUT, Fig1, 24 MHz & 48 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 48 MHz CLKOUT, 24 MHz CLKOUT, 48 MHz @48 MHz CLKOUT SSCOFF SEL1:0 = 10 SSC= 0.25% SEL1:0 = 11 SSC= 1.5% SEL1:0 = 01 Notes SSCOFF SEL1:0 = 10 SSC= 0.25% SEL1:0 = 11 SSC= 1.5% SEL1:0 = 01
0.4 V to 2.4 V
SSCCLKOUT = 24 MHz XIN = 48 MHz
Input clock frequency 10 -- 60 MHz *1,3 Stabilization time -- -- 2 ms Notes: 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.
SSCCLKOUT (or CLKOUT) tcycle n tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.6.00 Apr 07, 2006 page 4 of 8
HD151TS303RP
Application Information
1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type.
R1 SSCCLKOUT 1 8 SEL1 R2 VDD C2 C1 3 2 7 CLKOUT
TS300 Series
GND GND 4
6
SEL0
5
GND XIN (Crystal or Reference input) XOUT (Crystal or Not connection)
Notes:
C1 = High frequency supply decoupling capacitor. (0.1 F recommended) C2 = Low frequency supply decoupling capacitor. (22 F tantalum type recommended) R1, R2 = Match value to line impedance. (22 Reference value) Figure 2 Recommended circuit configuration
Rev.6.00 Apr 07, 2006 page 5 of 8
HD151TS303RP 2. Example Board Layout Configuration
VDD (+3.3 V Supply)
P FB
22 F
G
R1 SSCCLKOUT 0.1 F
G
1
8 R2 7 CLKOUT
G
3
6
4
5
Crystal connection or Reference input Note:
Crystal connection or Not connection
G Via to GND plane R1, R2 = Match value to line impedance. (22 Reference value) FB = Ferrite bead.
Figure 3 Example Board Layout
Rev.6.00 Apr 07, 2006 page 6 of 8
HD151TS303RP 3. Example of TS300 EMI Solution IC's Application
Spread Spectrum Modulated Clock XIN XOUT TS30X SSC CLKOUT Ref. Clock 3.3 V CMOS level ref. Clock CPU & ASIC XTAL Memory Graphics System Cont.
Figure 4 Ref. Clock Input Example
Spread Spectrum Modulated Clock
System BUS
XTAL
XOUT
TS30X SSC CLKOUT
CPU & ASIC
System BUS
XIN
Memory Graphics System Cont.
Figure 5 XTAL Ref. Clock Input Example
Rev.6.00 Apr 07, 2006 page 7 of 8
HD151TS303RP
Package Dimensions
JEITA Package Code P-SOP8-3.95x4.9-1.27 RENESAS Code PRSP0008DD-C Previous Code FP-8DCV MASS[Typ.] 0.085g
*1
D 5
F
8
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE E
*2
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e 4
*3
c
Reference Dimension in Millimeters Symbol
bp
x
M L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 4.90 5.30 3.95
0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.10 0.75 0.40 0.60 1.27 1.08
Rev.6.00 Apr 07, 2006 page 8 of 8
A
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